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UART.rar
- 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5,The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
uart.rar
- Verilog编写的UART程序源代码。测试成功。支持字符串发送,UART prepared Verilog source code. Successful test. Support string sent
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
uart
- UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
uart
- verilog编写的uart发送和接收的源代码。简单易懂。-verilog uart prepared to send and receive the source code. Straightforward.
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
mini-uart
- Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
UART
- 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
xapp341
- verilog uart for spartan 3 fpga, its great
uart
- verilog写的与电脑通信的uart，我实验过了，一切都很好，工作很好-verilog written communication and computer uart, I had the experiment, everything is very good, very good work
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
uart
- this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
uartverilog
- Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
uart
- verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
uart-code-Verilog
- uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
UART
- Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog