搜索资源列表
eeprom_i2c.tar.gz
- I2C EEPROM verilog simulation model,I2C EEPROM verilog simulation model
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包,包括Verilog源代码,Doc说明文档,仿真DDR芯片模型,仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
i2c_model.tar
- I2C EEPROM verilog simulation model
pll_verilog
- verilog model of a P-verilog model of a PLL
sdram_samsung
- 三星SDRAM的verilog模型的完整源码-Verilog model of Samsung SDRAM complete source
57578886i2c_slave
- i2c总线从模式的verilog实现 适合研究i2c的同志参考-i2c bus from verilog model for study of the realization of comrades i2c reference
spasion_flash_verilog_model
- verilog模型,用于仿真flash,可以快速地看懂-verilog model for flash controller specified for spasion flash, please download it look at it
Flash
- 三星flash编程Verilog程序,单页编程,支持K9K4G08芯片-Samsung' s flash programming Verilog program, single-page programming, support K9K4G08 chip
74hc74
- 带使能和清零端的D触发器,Verilog实现,有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
ds1621_latest.tar
- DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型,verilog实现,带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型,包括以下4个部分:RTL源代码,测试平台,软件仿真代码,说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
Verilog-Round-Robin-Arbiter-Model.tar
- Verilog Round Robin Arbiter Model
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
24xx02-Verilog-Model
- 24xx02 Verilog Model 在官网上下载的 eepROM 可以参考-Download on the official website 24xx02 Verilog Model eepROM can refer to
A-Verilog-Model-of-Universal-Sequence-Detector.ra
- a verilog model of universal seq detector
93xx66x Verilog Model
- verilog model for 93xx6xx
24xx04 Verilog Model
- verilog model for 24xx04