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16位串行输入,并行输出，运用verilog语言编写，已通过测试-16-bit serial input, parallel output, using verilog language, has been tested
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AD5399是一款串行输入、双通道、12位数模转换器，可采用二进制补码数字编码。。
用Verilog实现其配置与功能-AD5399 is a serial input, dual-channel, 12-bit DAC, digital code can be twos complement. . Configuration and use Verilog functions to achieve its
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对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
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verilog实现键盘驱动功能，具备基本字母按键输入，大小写转换功能，通过串口与主机实现交互-verilog to achieve keyboard-driven features, basic letter keys input, case conversion functions, interact with the host computer through the serial port
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LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
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用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
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implementing verilog code for parallel input and serial output.-implementing verilog code for parallel input and serial output.
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进阶实验_08_PS2_01 接受标准键盘输入，通过串口打印到PC，verilog-Advanced experimental _08_PS2_01 acceptable standard keyboard input through serial port to print to PC, verilog
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data path is serial input and data serial output for verilog code
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Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data
communication systems and other serial data transmission systems. CRC is based on
polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
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实现1024位并行输入，32位串行输出的verilog HDL程序 并带有其测试程序-Achieve 1024 parallel input, 32-bit serial output verilog HDL program and with the test procedures and serial converter
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用Verilog HDL编写的串口输入输出程序，可实现数据的传输，在DE2-70上测试通过，有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
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Verilog 编写全双工UART
input clk, // 这个模块的主时钟
input rst, // 同步复位信号
input rx, // 串口接收端口
output tx, // 串口发射端口
input transmit, // 发送信号
input [7:0] tx_byte, // 发送的字节
output received, // 表明，已接受到一个字节
output [7:0] rx_
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FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
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the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples.
the second file is a te
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bch编码模块，verilog程序，串行输入，串行输出-The BCH encoding module, Verilog program, serial input, serial output
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CC217编程序，verilog实现，串行输入串行输出-CC 217 program, to achieve Verilog, serial input serial output
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一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, le
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自己编写的高效8位输入串行CRC-8 ATM程序(an effective program for 8bit serial input CRC-8 ATM calculate.)
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设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求：
（1）用状态机方法设计；
（2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
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