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daima.用VHDL语言设计一个数字秒表
- 用VHDL语言设计一个数字秒表： 1、 秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。 2、 计时精度为10MS。 3、 复位开关可以随时使用，按下一次复位开关，计时器清零。 4、 具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
UniversalRegister
- 普通的缓冲器 这种设计是一个普通的缓冲器，可以做一个直接的缓冲器，也可以做一个双向的转移缓冲器，还可以做一个递增的计数器和递减计数器-Universal Register This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
ud12
- this project is counter 12 bit up/down in vhdl to aldec enviroment .
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga
Downcounter
- Down Counter Exampled written in VHDL.
TB_Example_for_Students
- test bench for up down counter
counter
- Source code of a up/down counter in VHDL
asagi_yukari_sayici_entity
- vhdl up down counter, entity,vhdl, good source code
CounterUni
- Universal counter written on VHDL in Quartus II. It counts up and down by taking into account overflow and onderrun bits.
HW3
- Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d
behavioral_counter
- -- This example implements a behavioral counter with load, clear, and up/down features. -- It has not been optimized for a particular device architecture, so performance may vary. Altera recommends using the lpm_counter function to implement a co
lcdcounter
- vhdl code for the counter program that can be used to count down and count up
hw3
- Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d
AssignmentP7
- 1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated.
up_down_cntr
- vhdl code for up down counter
counter
- Up Down counter FPGA, VHDL
syncup_dn
- VHDL CODE FOR SYNCHRONOUS UP/DOWN COUNTER
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is