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wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : U
pci.tar.gz 完成WB BUS和PCI bus之间的传输
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transact
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
pit_latest.tar
- Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
wb_lcd
- 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
led_driver
- LED display verilog code. to generate clocks and wishbone interface
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
wb_conbus
- wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
verilog
- PCI/WISHBONE bridge Reference Design-PCI/WISHBONE bridge Reference Design
wishbone-slave-and-master-to-avalon-bus
- wishbone slave and master to avalon bus verilog
Wishbone
- wishbone总线的一些研究，包括一些代码-wishbone verilog
verilog-arbiter.tar
- Verilog arbitrator for Wishbone R3 compliant bus
i2c_wishbone.tar
- verilog i2c master wishbone slave wrapper