资源列表
music_1
- 这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player
handshake
- AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
testbench
- 利用system verilog写仿真测试程序，详细介绍system verilog的语法，及教程 -use system verilog write testbench
crc
- 非常不错的CRC冗余纠错编码Verilog源码-非常不错的CRC编码Verilog源码
I2C_rw
- 读写I2C FLASH的Verilog程序 -The Verilog program to read and write I2C FLASH
I2C_Slave
- I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
e1_vhdl
- 用VHDL在FPGA内部实现E1的接口，适合通讯相关专业硬件开发使用-Within the FPGA implementation using VHDL E1 interface, the hardware for communications-related professional development to use
fft
- 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
user_logic_0
- 基于microblaze EDK 工程，实现六种RFID 协议的ip core。-Based on microblaze EDK project, to achieve the six RFID protocol ip core.