资源列表
RomNCO
- 基于NCO的数字控制振荡器。带测试程序，输出12位的COS和SIN波形。-Based on the digital control oscillator NCO. With test procedures, the output 12 of the COS and the SIN waveform.
pci_core.tar
- vhdl 写的 PCI IP核程序，已经过测试-pci ip core
48_order-FIR-filter-with-8-folder
- 该代码是设计一个48阶FIR滤波器的文档，该设计方案主要运用了数字信号处理VLSI实现中的折叠的方式。-The code is a 48-order FIR filter design document, the main use of the design of VLSI implementation of digital signal processing in the way of folding.
verilog
- 基于Verilog HDL的通信系统设计一书的电子教案，里面有很多例子，大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
sdram_models
- MICRON公司SDRAM的各种仿真模型，可以用于各种仿真环境-sdram simulation model
LABVIEW制作的电子时钟软件
- 电子时钟软件，使用LABVIEW制作的电子时钟软件具有优美的界面-Electronic clock software, produced using the LABVIEW software electronic clock with a beautiful interface
EDA
- 移位相加8位硬件乘法器电路设计,该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。-Add 8-bit hardware multiplier shift circuit design, the multiplier is composed of 8-bit adder to temporal order, 8-bit multiplier design.
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
hdlc_decode
- 基于Verilog的HDLC解码器。其中时钟的提取采用数字锁相环-The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
Booth_4
- 用VERILOG 编写的弹球游戏，其中涉及到VGA协议和接口开发设计-Written with the VERILOG pinball game, which involves the development and design VGA protocols and interfaces
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch