资源列表
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
AD9708
- AD9708是高速AD转换芯片，采用VHDL实现10MSPS高速AD数据采集-AD9708 is high speed a/d conversion chip,10MSPS,using VHDL
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
lms
- verilog编写的lms算法模块，简单易用-lms module using verilog.It s simple.
HCIUART
- 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
FPGA_DSP_using_matlab
- 这是一个使用matlab语言来实现FPGA的DSP算法的例子。主要是针对xilinx的FPGA芯片。这是一种比较新的编程方法，让matlab工程师也能快速的进行硬件编程。-This is a language to use matlab to implement FPGA-DSP algorithm for example. Mainly aimed at xilinx FPGA-chip. This is a relatively new programming method, so that
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
FPGA_common_idea
- 本文讨论的四种常用FPGA/CPLD 设计思想与技巧：乒乓操作、串并转换、流水线操作、数据接口同步化，都是FPGA/CPLD 逻辑设计的内在规律的体现，合理地采用这些设计思想能在FPGA/CPLD 设计工作种取得事半功倍的效果。-This article discusses the four commonly used FPGA/CPLD design ideas and techniques: ping-pong operation, strings, and conversion, pipe
hamming_encodeadecode
- 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and
LCD
- DE2板上的LCD显示器驱动程序和相应的测试程序,verilog语言写的。-DE2 LCD display driver board and the corresponding test procedures, verilog language to write.
ADPCMverilog
- ADPCM编码的Verilog编码实现，代码有详细的注释，编译通过-ADPCM coding Verilog code, the code has detailed notes, compiled by
eMMC-CardStandard
- eMMC 多媒体卡协议标准完整版。网上无法找到，再次独家发布。-eMMC multimedia card protocol standard full version. Alone this one.