资源列表
verilog-example
- 4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器-failed to translate
FPGA-LDPC
- 用FPGA实现使用LDPC编码器和译码器-FPGA implementation by using LDPC encoder and decoder
ddsVHDL
- fpga实例 包含很多使用的例子 累加器 乘法器 触发器等-FPGA example real Verilog HDL
pll(FPGA)
- 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
LCD
- LCD1602的程序，只需改一改显示常量就可以！在ISE中调试成功-LCD1602 process, just simply show the constants can be! Successful commissioning of the ISE
CRC
- 这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
micro.logic
- 16通道逻辑分析仪（xilinx XC3S50AN-4TQ144C +CY7C68013A-56PVXC）pcb图纸 使用altium 08打开-schdoc+pcbdoc
ES8388-DS
- 低功耗立体声音频编解码器 带耳机放大器 ES8388是一种高性能，低功耗和低成本的音频编解码器。它由2通道ADC，2通道DAC，麦克风放大器，耳机放大器，数字声音效果，并模拟混合和增益功能。-Low Power Stereo Audio CODEC With Headphone Amplifier ES8388 is a high performance, low power and low cost audio CODEC. It consists of 2-ch ADC,
music_player
- FPGA实现音乐播放器，蜂鸣器播音，LED点阵屏同步滚动显示歌词，与音乐同步效果好，按键控制播放、暂停、停止、重播。-FPGA realization of music players, broadcasting buzzer, LED dot matrix display screen, synchronized scrolling lyrics and music synchronization effect, buttons control play, pause, stop, repla
sram
- 用FPGA 控制sram读写程序的小程序，-fpga control precedure
SystemVerilog_2nd.pdf
- System Verilog 验证设计。主要讲如何编写测试用例。设计数字电路比较经典的教程。-System Verilog design verification. Mainly about how to write test cases. Digital circuit design more classic tutorial.
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts