资源列表
fpga-jpeg
- 基于FPGA的JPEG图像压缩,实现JPEG图像的实时压缩-FPGA JPEG compress
spasion_flash_verilog_model
- verilog模型,用于仿真flash,可以快速地看懂-verilog model for flash controller specified for spasion flash, please download it look at it
image_enhacement_fpga
- Image Enhancement algorithms implemented on FPGA in the literature. Papers are added.
Test_Plg_18
- 基于FPGA的等精度频率测试仪,测量范围1HZ到100M.已调试成功.采用康芯公司的FPGA开发板,嵌入51内核程序.-FPGA-based test instrument such as the frequency accuracy, measurement range 1HZ to 100M. Has been a successful debugging. Using Kang' s FPGA core development board, embedded in 51 kernel
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真, synplify综合,并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
i2c
- FPGA实现的I2C总线源代码,调试通过,是我用了几年的一个程序包-FPGA implementation of the I2C bus, the source code, debugging is passed, I have used it for few years .
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器,调用的内部核,其特色是可以用较少的资源实现该功能,而且可以实现参数重载,即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p
chuankou
- FPGA和单片机的串口通信资料,本代码是用VHDL写的。-FPGA and the microcontroller serial communication of information, the code is written in VHDL.
verilogforelevater
- 本代码主要用于实现利用verilog编码八层电梯的自动控制。利于初学者学习参考-This code is primarily used to implement the use of automatic control verilog coding eight-story elevator. Reference to help beginners learn
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO,并通过串口发送数据初始化FIFO,FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
DS1302
- 本代码是控制DS1302的VHDL代码,浅显易懂,方便修改,注意看data sheet,保证时钟和各个延迟满足要求即可-This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays