资源列表
PWM-OUT
- 这里是一个比较好的用Verilog写的通过按键控制PWM输出从而控制小灯亮灭程度的经典例子~！~-Here is a better written in Verilog by using buttons to control the PWM output level of the control of small lights eliminate the classic example of ~! ~
DAC_TLV5616
- tlv5614的驱动程序，用verilog语言编写的，fpga芯片为altera公司的ep2c35。 调试成功放心使用-tlv5614 driver, using verilog language written in, fpga chips altera company ep2c35. Assured the success of the use of debugging
AlteraSdramIP
- Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
cordic_latest.tar
- Cordic Core Specification
cpsk
- 用VHDL硬件语言对BPSK调制解调系统进行编写，仿真通过，源代码-VHDL hardware language using BPSK modulation and demodulation system, the preparation, simulation adopted, the source code
Design_and_Analysis_of_Electronic_Code_Lock
- 电子密码锁的设计与分析__系统设计要求/系统设计方案/主要VHDL源程序/系统仿真/硬件验证/设计技巧分析/系统扩展思路-Design and Analysis of Electronic Code Lock
viterbi5
- implemented viterbi in vhdl
MatchFilter
- VHDL语言实现8路并行输入，8路并行输出，直接序列扩频接收机的高速匹配滤波。 -VHDL language to achieve 8-channel parallel input, 8-channel parallel output, high-speed direct-sequence spread spectrum matched filter receiver.
SCRAMBLER
- 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
BALANCEBALL-Finale
- 重力感应小球游戏，基于FPGA平台，Verilog语言，VGA输出。-Gravity sensing ball game, based on FPGA platform, Verilog language, VGA output.
count100
- 一个用VHDL语言编写的一百进制计数器。软件平台是Quartus II 7.2 ，由前面设计的小模块组合起来制作的，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a binary counter 100. The