资源列表
vhdljiaocheng
- 献给有志于学好FPGA软件的人。这是一本VHDL的电子版教程，写的很详细，希望对各位有所帮助。-FPGA dedicated to those who want to learn software. This is an electronic version of vhdl tutorial, written in great detail, and they hope to help you.
floating_point_adder
- 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
spiflash_ctrl
- VHDL 语言实现的SPI FLASH的读写-VHDL language to read and write of the SPI FLASH
mul24x24
- 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit
qda
- 三路智力竞赛抢答器，利用VHDL设计抢答器的各个模块，并使用EDA 工具对各模块进行仿真验证。智力竞赛抢答器的设计分为四个模块：鉴别锁存模块；答题计时模块；抢答计分模块以及扫描显示模块。把各个模块整合后，通过电路的输入输出对应关系连接起来。设计成一个有如下功能的抢答器： （1）具有第一抢答信号的鉴别锁存功能。在主持人发出抢答指令后，若有参赛者按抢答器按钮，则该组指示灯亮，数码管显示出抢答者的组别。同时电路处于自锁状态，使其他组的抢答器按钮不起作用。 （2）具有计分功能。在初始状态时，主持
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
dianti
- 用verilog写的电梯控制器内附测试文件和实验报告 -Use verilog to write elevator controller with the test documentation and test reports
v5_config
- xilinx v5的在线，上位机配置程序-xilinx v5 configuration
CPUVHDL
- CPU+VHDL代码及详细注释\一个老外写的 200多行代码-CPU+ VHDL code and detailed notes \ a foreigner wrote more than 200 lines of code
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
Testbenching-Example
- FPGA设计测试用例介绍PPT文档，对于初写测试用例很有帮助。-FPGA Design of test cases to introduce PPT files, helpful for the beginning of writing test cases.