资源列表
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
LCD
- verilog语言编写的LCD读写代码，包括整个工程-read and write languages LCD verilog code, including the entire project
virtual_keyboard
- 通过PS2口连接键盘与FPGA，按动1-7数字键达到虚拟电子琴的效果-PS2 keyboard port connect to the FPGA ，press the number keys 1-7 to reach the effect of the virtual keyboard
POWER-48to24
- 48V转24V 100W开关电源 DC-DC-Switch to 24V 100W 48V DC-DC switching power supply
Counter
- 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
VHDL
- 很详细的vhdl教程，能够帮助大家很好的学习fpga，希望能够帮助大家学习。-Vhdl tutorial is very detailed, very good to help people learn fpga, hope to help you learn
3333
- 可编程单脉冲发生器,各模块已经写好，调试运行并通过-Programmable pulse generator, the module has been written, debugging and running through
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
IR
- 来自著名公司半导体公司IR的基于FPGA的AC伺服电机设计-FPGA based AC Servomotor-Control Designs from IR
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output