资源列表
AD_sample_100Mhz
- 用Verilog编写的FPGA AD采样 用Verilog编写的FPGA AD采样-AD_sample_100Mhz
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
uart_16550
- 一个简单的UART源代码，速率可以上到115200，具体看参考时钟-A simple UART source code, the rate can be up to 115200, see the specific reference clock
dcfifo_design_example
- ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
adda
- TLC549进行模数转换后在通过tlc5615数模转换出来！结果下载证明可用-TLC549 analog to digital conversion digital-analog conversion through tlc5615 out! The results prove that is available to download
verilog-vga
- Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF a
cordic
- 在QUARTUS环境下，通过Verilog实现cordic，产生sin，cos-In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
17_walsh_128
- walsh码，在CDMA系统中经常使用到的方法，在quartusII环境下实现的。-walsh code in the CDMA system, the method often used in quartusII environment to achieve.
pci9054
- PCI读写控制程序 PCI9054与SRAM连接-PCI9054 PCI read and write control procedures connected with the SRAM
xie
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
ANSWER
- 采用VHDL设计的抢答器，抢答时间10秒钟，10秒内无人抢答，则抢答按键失效。显示抢答的队伍号。适合做课程设计。-Design using VHDL Responder, Responder for 10 seconds, no answer in 10 seconds, then the answer in key failure. Display answer in team numbers. Suitable curriculum design.