资源列表
ahb_master1
- AHB master 关于ahb总线协议中的master的encode -AHB master
risc8
- 基于verilog的8位risc-cpu源码，modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
74LS148
- 用vhdl语言编译一个优先编码器74LS148-vhdl 74LS148 code
codelock7(0)
- Altera的DE2板子的一个简易密码锁，引脚信号已经引入，在实验板上调试通过-Altera' s DE2 board a simple password lock pin has been introduced by the experimental board debugging
uart_test
- Verilog 基于FPGA的直接RS232串口测试-Verilog FPGA-based test of direct RS232 serial port
frame detect
- 帧同步搜索电路，检查帧同步所在，VHDL程序-frame detect
vhdl
- 键盘去抖，电子密码锁，键盘输入去抖vhdl语言程序-Keyboard debounce
controller-design-of-sdram-
- 基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
DCM
- 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
FPGA_constraints
- 这是关于FPGA时序约束的文档，属于入门级介绍。在逻辑设计尤其是高速设计时，时序约束是必不可少的！-This is the documentation on the FPGA timing constraints, are entry-level introduction. High-speed logic design, especially in the design, timing constraints is essential!
Each-module-program
- 此程序为基于FPGA乐曲演奏电路设计的VHDL程序，可根据程序手动控制播放的音乐-This program tracks performance FPGA-based VHDL circuit design process, according to the manual control of the music program
FPGA
- 视频压缩技术研究及FPGA实现探讨 视频压缩技术研究及FPGA实现探讨-Video compression technology and its FPGA implementation of video compression technology and its FPGA implementation of