资源列表
dll
- 在传输数字信号的时候，需要时钟定时，本程序可以从数据中恢复出时钟-In the transmission of digital signals, the need for clock timing, the program can recover a clock from the data
yt7132_clock
- 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system
3_3_mean_diltter(ALU)
- 3*3均值滤波的VHDL语言实现的工程，对红外图像进行有效的去噪处理。这是其中的ALU模块，专门用来测试其延迟状况的模块。-3* 3 mean filter VHDL language works effectively on the infrared image denoising. This is one of the ALU module, designed to test the status of the module delay.
chuzuche
- FPGA出租车的制作最终程序,实现自动计价功能。-The production of the final program FPGA taxi, automatic pricing feature.
gradtobin
- 格雷码转二进制的程序（verilog），经过验证quartus、8.1-grad to binary
keeloq encoder
- this code is a keeloq encryption verilog code-keeloq encryption verilog code
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
XAPP134_SDRAM_VHDL
- XAPP134 SDRAM VHDL design file
XAPP134_SDRAM_Verilog
- Xilinx XAPP134 SDRAM Verilog
taxi-money
- 使用verilog编写，实现出租车计价器得日常计费功能-Prepared using verilog achieve Taximeter daily accounting functions have
ads7809
- ADS7809是Burr-Brown公司推出的高精度AD采集芯片。它采用5V单电源供电,内含16位 逐次逼近寄存器,采样精度高,功耗小。 用Verilog实现其配置-ADS7809 is a Burr-Brown Introduces High Precision AD capture chip. It uses a single 5V supply, with 16-bit successive approximation register, sampling and high pre
FPGA-basign
- 基于FPGA的医学超声成像数字波束合成器设计FPGA-based digital medical ultrasound imaging beamforming design-FPGA-based digital medical ultrasound imaging beamforming design