资源列表
Verilog_FPGA_DDS
- Verilog编写基于FPGA的DDS实现-FPGA-based DDS Verilog
fa0fdm
- 这是很有用的VHDL和VERILOG 的源代码，我是买过的来的，觉得太有用了，特此共享，对于学习OFDM的人来说，是太难得了！-This is useful VHDL and VERILOG source code, I bought in the past, I feel so useful, and hereby share, for the people who study and OFDM, is too hard won!
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
sramceshi
- 用VERILOG编写的测试SRAM代码，已通过板级测试，完整无误-SRAM with the VERILOG code written test, have passed the board-level test, complete and correct
xapp921c
- Xilinx的ddc duc的文档 xapp921c-xapp921c
ADCTR
- 基于VHDL实现AD7891转换时序的控制器-perfect progranm by vhdl
recovery
- 恢复时钟信号的代码,用于数字通信中，used to recovery the timing from data-used to recovery the timing from data
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
7_1LVDS_serilizer
- 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency a
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
DS18B20ss
- 使用fpga硬件语言写的DS18B20程序，altera的fpga，单总线测试可用-altera fpga ds18b20
cop2000
- 模型机仿真的VHDL语言描述，在xilink9.1环境中实现。-VHDL simulation model of machine language to describe, in xilink9.1 environment implementation.