资源列表
Channel_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
IFFT11111
- 使用Verilog编写的IFFT，ISE12.2下编译通过，学习IFFT核的同学可以参考-Use of the IFFT in Verilog compiler, ISE12.2 under study IFFT core students can refer to
Viterbi11111
- 使用Verilog编写的vertbi译码模块，ISE12.2下编译通过，主用是调用ISE下的Vertibi核设计实现的。-Written using Verilog vertbi decoding module, ISE12.2 compiled by the main use is to call ISE the nuclear Vertibi designed to achieve.
reaction-time_FPGA_Verilog
- 基于FPGA的反应时间测试机——verilog HDL-Based on the reaction time test machine in the FPGA- Verilog the HDL
Verilog-HDL-digital-system-design
- Verilog HDL数字系统设计教程,其中对Verilog HDL语言的语法，FPGA的结构及其应用作了详细的讲解-Verilog HDL digital system design introduces the Verilog HDL language and the FPGA function including syntax ,FPGA frame and application and so on
uart-of-fpga
- FPGA实现UART通信程序，verilog hdl语言实现的，好用-UART of FPGA
geleima--10
- 格雷码计数器 vhdL实现 quartus编译通过-Gray code counter VHDL quartus compiled by
TURBO_2964
- 本程序只进行了2964 帧长的TPC编码-CtransfDlg::OnEncodeTPC2964(CString SrcFile,struct PARAMETER*PARAMETERDEAL)
CIC-UPSAMPLE
- CIC内插 内插系数可变，阶数1~6,Verilog版本-Inserted within the CIC interpolation factor variable, the order of 1 to 6, the Verilog version
4613m73a_nand_model
- File Descr iptions: --- --- --- nand_model.v -structural wrapper for nand_die_model nand_die_model.v -nand model of a single die nand_defines.vh -file used to generate correct port maps for nand_model instanciation. nand_parameters.vh -fi
rom
- 此包里有两个程序，其一为ROM存储器，其二为8位加法器-This bag has two programs, one for the ROM memory, and the second 8-bit adder
screw
- 基于FPGA的串行数据加解扰代码，用VHDL实现，可跑400M的速度。-FPGA-based serial data plus descrambling code using VHDL, and can run 400M speed.