资源列表
frame-synchronous-search-circuit
- 用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame lengt
Waveform-generator(DAC902)
- 信号发生器可1Hz - 10MHz 可调频调幅产生ASKPSK-Waveform generator(DAC902)
time
- fpga万年历 vhdl语言 能实现现实时分秒年月日 及闰年判断 整点报时-every second when the fpga calendar VHDL language can achieve real date and leap year to judge the whole point of time
DataCycle
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineCPU
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
VHDL_Snake_Game
- 在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码-Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source
deng
- HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示-HDL Verilog electronic code lock input errors have prompted alarm input is correct
FPGA
- FPGA应用开发典型实例之片上硬件乘法器的使用-The use of FPGA application development typical example of on-chip hardware multiplier
64FFT(VHDL)
- 用VHDL语言实现64点的FFT,包含源程序和一篇论文-64-point FFT with VHDL contains the source code and a paper
pcm
- ２４选８多路选择计数器 PCM编解码,采编器VHDL 源代码，包括顶层文件。-PCM(Pule code modulation) code and decoder
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
FPGA-LCD
- 利用FPGA，结合NIOS方案，驱动TFT4.3寸屏并显示。-Use of FPGA, combined with NIOS scheme, drive TFT4.3 inch screen and display.