资源列表
test
- 利用VHDL 编程AD9910 产生DDS -Use of the VHDL programming AD9910 DDS
count_zj
- 基于FPGA的数字锁相环中环路滤波器的设计-FPGA digital PLL loop filter design
MCP4822
- SPI recever avr programing
MANCHESTER-ENCODING
- manchester encoding 波形-software for manchester encoding
digital-signal-processing-with--fpga
- 数字信号处理用FPGA实现，其中包含常见的FFT，滤波器，自相关等用VHDL和Verilog语言实现的-digital signal processing with fpga
FPGA_ad2s82
- 双通道AD2s82测角系统的FPGA控制器实现-FPGA controller for dual-channel AD2s82 angle measuring system
Active-power-filter
- 有源电力滤波器，用于实现无功治理与谐波补偿，精度很高-Active power filter for reactive power control and harmonic compensation, high accuracy
jpeg-codec-in-verilog-HDL
- jpeg codec in Verilog HDL.-jpeg Code decoding used by Verilog HDL。
Rwummayiie
- 研究了传统误码仪的工作原理与结构，并运用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能，，如LCD显示出来驱动driver，串口通信驱动driver，误码测试，数据存储芯片驱动driver等功能. -Study the working principle and structure of the traditional BERT, and the use of VHDL language to simulate most of the traditional BERT fu
VPD__using_FFe
- verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
DDDCCT_IDCTi
- 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包含VHDL及及Verilog版本。可用途JPEG及MEPG压缩算法 已通过测试。 -The discrete cosine transform and inverse discrete cosine transform HDL code and test files. Contains VHDL and Verilog versions. Can use JPEG and MEPG compression of algorithm has
verilog-compiler
- 本文包含了几个关于Verilog的编译器的源码实现，适用于深入学习Verilog的读者-This article contains several Verilog compiler source for in-depth study of Verilog reader