资源列表
Turbo_Encoder_Decoder
- The turbo enocoder and turbo decoder is design in VHDL code.
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
switch_fabric
- verilog 写的具有代数交换功能的数据交换，是交换机设计的核心部分。-Switches Core by Applying Algebraic Switching
ad5544
- 模数乘法器AD5544的Verilog源程序，已在项目中验证了其可行。-Verilog source AD5544 analog multiplier, and have verified its feasibility in the project.
ad5764
- 数模转换器AD5764的Verilog HDL源程序，已在项目中验证了其可行。-DAC AD5764 Verilog HDL source code, and have verified its feasibility in the project.
code
- 基于FPGA的乘法器译码器程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-FPGA multiplier based procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
SP_SCH(Executable)
- 调度器一般包括SP、RR、WFQ等，SP调度指的是绝对高优先级调度，此种调度不带权重概念，按照优先级进行调度。四个按键作为端口有效指示，2个LED发光二极管指示此时调度的端口号，可以按下KEY3按键，按下按键代表当前按键输入无效，然后观测LED，没有按下的时候LED1 LED0都发光，按下KEY3按键的时候LED1发光 LED0不发光，代表此时调度端口为2，不按下时候代表调度端口为3。 -The scheduler typically include SP, RR, WFQ, etc., SP
AD80305
- 一种基于xilinx FPGA S6,verilog 实现AD80305输入输出接口配置，可参考-Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
data_switch
- verilog 实现15bit数据与176bit数据间的相互转换，可根据此代码作一定的修改，可以实现其他位宽数据的转换-verilog to achieve mutual conversion between 15bit data with 176bit data can make certain changes based on this code, you can achieve the conversion of other bit-wide data
猜數字，終極密碼
- verilog code 可以控制玩家數目，及遊戲模式(有兩種:猜數字 + 終極密碼) 最後結果會顯示出排名及分數
RR_SCH(Executable)
- FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
TCAM
- FPGA VERILOG TCAM (ternary content addressable memory)是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。-FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.