资源列表
renyi
- 基于FPGA的任意波形发生器的设计源程序-Achieve arbitrary waveform generation
QPSK
- modelsim环境下QPSK解调电路的仿真-modelsim simulation environment under QPSK demodulation circuit
SPWM-pulse-control-program
- fpga程序，用于逆变器的SPWM控制，有保护程序，包括脉冲闭锁保护，有注释，非常好用-fpga program for PWM inverter control, there are savers, including pulse lockout protection, notes, very easy to use
sd_ctrl
- Verilog写的基于FPGA的SD卡的读写程序，能够读出SD卡中存储的数据-Write Verilog FPGA-based SD card reader program, it is possible to read out the data stored in the SD card
CLK_DIV_IP_packager
- Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
verilog
- 数字信号处理的FPGA实现(第3版) verilog源码-FPGA digital signal processing (3rd Edition) verilog source
IQ_SIGNAL_GENERATION_CODE
- IQ信号发生器_好用_测试正确,项目已经使用-IQ signal generator _ with _ test correctly
TLV5630ceshi
- TLV5630 DA转换芯片FPGA控制程序源代码，verilog编写-TLV5630 DA converter chip FPGA control program source code, verilog prepared
FPGA_BDPSK
- FPGA实验_BDPSK调制解调器设计(包含10个模块)-Experimental _BDPSK modem FPGA design (including 10 modules)
TCD1304_drive
- FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机-FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial
pingpong
- 用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作-Verilog pingpong
Cymometer
- 用FPGA设计的等精度测量频率。频率的测量范围为1Hz-100MHz。可以测占空比，测时间间隔等。可测正弦波和方波。精度大于10e（-4）-Using FPGA to design the equal precision frequency measurement.Frequency of the measuring range is 1 hz- 100 MHZ.Can examine duty ratio, time interval measurement, etc.Sine wave an