资源列表
Transmitter
- 基于hdl的ofdm基带处理器发射机的设计与实现 包括 工作时钟 主控单元 导频插入 长短训练序列生成 data符号调制 循环前缀与加窗处理 IFFT/FFT 信道编码 扰码模块等-Hdl of ofdm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence g
i2c_6114
- 使用FPGA对NVP6114进行配置！绝对原创，已经成功应用到AHD高清监控机上。代码为纯VHDL编写，不是软核的。-Using FPGA to configure NVP6114! Absolutely original, has been successfully applied to the AHD high-definition monitor system. Write code for pure VHDL, not NIOS or MicroBlaze.
I2S-Serial-communication
- 这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
CH376
- 用VERILOG HDL语言写的usb程序。FPGA芯片用的是ALTERA公司的，编程所用的软件为quartus和nios，USB芯片为CH376.-VERILOG HDL language written with usb program. ALTERA FPGA chip using the company s software program used quartus and nios, USB chip CH376.
USB_save
- 这是基于FPGA的USB通讯程序。通过在quartus中建立SOPC，建立PIO口，并在NIOS中写驱动和寄存器等，实现USB通信。经检验，该程序通信正常。-This is FPGA-based USB communication program. By establishing the quartus in SOPC, establish PIO mouth and NIOS to write drivers and registers, realize USB communications.
8b10b
- 8b10b编解码代码，可以实现8b10b的编码及解码-8b10bencode deccode
RISC-CPU
- 精简指令集 16位流水线CPU 可实现硬件模拟-16-bit pipelined RISC CPU hardware emulation can be achieved
Project
- 这是一个关于cache的verilog代码，有icache和dcache的实现-a verilog code about the cache including i cache and dcache
cycle_en_decoder
- 卷积码编码/解码，Verilog语言实现，带仿真程序。-Convolution encoder/decoder, Verilog language, with a simulation program.
fpga_pid
- 在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立-PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors
three_ADF4350_verilog_code
- 该verilog代码实现对三个ADF4350的控制，并附带一个测试程序。-The Verilog code to achieve control of the three ADF4350, with a test program.
K7_1M
- 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping