资源列表
12bityiweijicunqi
- 基于quartusii的vhdl12位指数清零移位寄存器,可以用于实现任意序列流水灯等程序功能-Quartusii based index of vhdl12 bit shift register is cleared, any sequence can be used to implement water lights and other program features
sdram_ov7670_rgb_vga_640480
- C:\01_FPGA\3高级实验篇\摄像头OV7670模块采集图像并在显示器上显示-C: \ 01_FPGA \ 3 senior experimental papers \ OV7670 camera module to capture images and displayed on the monitor
NIOSII_TFT
- 基于altera公司fpga的niosii软核实现的tft彩色显示屏显示SD卡图片,可用于实现幻灯片功能-Niosii company based soft-core altera fpga implementation tft color display SD card images can be used to implement the slideshow feature
Ycbcr444-to-Ycbcr422-example
- Ycbcr444 转 Ycbcr422 的源码-the Verilog code of Ycbcr444 to Ycbcr422 example
HSMB
- 基于Altera平台的SFP+光模块硬件代码-Based on Altera Platform, provided a 10G Optic XAUI to SFP+ controller
DE1_SoC_Audio
- 声音录制、播放的Verilog代码,用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
snake
- Verilog语言编写的贪吃蛇程序,使用VGA显示,PS2键盘控制。-Snake program written in Verilog, using the VGA display, PS2 keyboard control.
SPWM
- ALTERA FPGA上采用Verilog语言实现查表法产生三电平SPWM-Produce three-level SPWM by look-up table
CfgDDS_9910
- dds ad9910配置的verilog hdl程序,模块化设计,输入待配置的数据,字长,启动信号,即可自动产生时序,完成一次配置,模块还有done握手信号,方便用户调用时,反复多次配置。-dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatical
ADS1278
- ADS1278 8通道ADC数据采集程序,AD采样深度24bit,保留16bit输出。状态机编写。-ADS1278 8-channel ADC data collection procedures, AD sampling depth of 24bit, 16bit output reserved. Write state machine.
VHDL
- 设计一个具有进位输入和进位输出的8位行波进位加法器-8-bit ripple carry adder design having a carry input and a carry output
sonic
- 基于FPGA的超声波测距,通过数码管显示距离-FPGA-based ultrasonic distance