资源列表
华为_大规模逻辑设计指导书
- 本文为华为公司内部FPGA开发资料，对提升编程能力有较大帮助。(This paper has a great help for improving the programming ability of HUAWEI's internal FPGA development data.)
Edege_detect
- 边沿检测模块，实际项目中验证； 功能：上升沿、下降沿检测(Edege detect module Func : rising_edge falling_edge detect)
eetop.cn_kc705
- Xilinx PCIE IP核的应用例程，带DMA，有V6和KC705的应用(Xilinx PCIE IP DMA example)
27_sdram_ov5640_sobel_vga
- 按键控制，vga显示，数码管显示，读取sd卡(Key control, VGA display, digital tube display, read SD card)
有符号小数乘法器
- 改进的verilog乘法器，改进了此项乘法，更利于在硬件中的使用(introduce this funcation in this code.)
ADC088S102
- 用于FPGA的实现ADC088S102多路采集功能的Verilog源码(Verilog source code of the function of ADC088S102 multichannel collection for FPGA.)
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
spiflash
- SPI接口实现，对SPI写，擦出等功能操作，此代码在板子上进行验证过，没有任何问题(SPI interface implementation, write to SPI, wipe out and other functional operations, this code has been verified on the board, there is no problem.)
LaSaNewNB_M88E1111_TCP1000mhz
- 用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核(With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core)
ALU32
- 采用booth算法，实现了32位的ALU。(The 32 bit ALU is realized by using the Booth algorithm.)
北航MIPS多周期
- 多周期流水线处理器的verilog实现。(The Verilog implementation of a multi cycle pipelined processor.)
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio