资源列表
EDA
- 本设计是在Quartus ii开发环境下采用VHDL语言实现的AMI/HDB3编码器课程设计。(This design is a course design of AMI / HDB3 encoder implemented by VHDL language in the development environment of Quartus II.)
CDCM6208_SPI
- 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
2FSK调制解调的FPGA实现（VHDL）
- 2FSK调制解调的FPGA设计，基于XINLINX的ISE平台开发，采用VHDL语言设计，有设计文档，欢迎学习借鉴(The FPGA design of 2FSK modulation and demodulation, based on the ISE platform of xinlinx, is designed with VHDL language, with design documents, welcome to learn)
S02《Artix7修炼秘籍》MIG_DDR内存应用
- artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
模24计数器
- 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)
单周期CPU大作业-2020
- Verilog projects cpu
分频器的modelsim仿真
- 这是分频器的modelsim仿真文件源代码，这是分频器的modelsim仿真文件源代码，这是分频器的modelsim仿真文件源代码
POC
- 实现了计算机系统中作为I/O模块的POC。(It simulates the POC module which works as an I/O module in a computer system.)
drsstc
- 实现SKP/PDM功能的drsstc工程文件(DRSSTC project file for SKP / PDM)
Verilog的150个经典设计实例
- 非常有用的verilog的150个经典编程实例(150 classic programming examples of Verilog)
DPWM
- 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
crc16
- verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)