资源列表
ac620_calculator_key_board
- 基于Verilog编写的计算器，使用矩阵键盘输入数据，使用数码管显示运算过程和结果，基于小梅哥AC620开发板验证通过(The calculator based on Verilog uses matrix keyboard to input data and digital tube to display the operation process and results. The development board based on little mac620 passed the veri
DDR2_SDRAM操作时序
- DDR2_SDRAM操作时序，介绍的很详细，不错(DDR2? SDRAM operation sequence, very detailed introduction, very good)
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
TMP75读写
- TMP75的读写代码，包括时钟控制、读数据和配置。
现有16位寄存器。初始值为0
- 现有16位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16位寄存器对7求余的余数data_out[20]。(Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data wil
FSM状态机verilog代码
- 能实现状态转换、移位功能的状态机，使用verilog代码编写，能通过modelsim编程实现。
ZYNQsl
- FPGA开发教程，含开发手册和源代码，例程齐全，很好的FPGA学习资料(A tutorial on the development of FPGA, including development manuals and source code, has complete routines and good learning materials for FPGA.)
formal_verification
- 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
单周期CPU实验报告
- 单周期CPU的设计思路(包含数据通路、指令集、信号的设计)(Design Ideas of Single Cycle CPU)
forug_2016.03
- formality2016 userguide
milian
- 源自米联平台开发板的为文档及教程，内部含有部分关键代码，可复制粘贴。(Documentation and tutorials from milian platform development board)
eetop.cn_专用集成电路设计实用教程
- 本书的主要对象是IC设计工程师，帮助他们解决IC设计和综合过程中遇到的实际问题。(The main object of this book is IC design engineers, to help them solve the practical problems encountered in IC design and integration.)