资源列表
password_lock
- 电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
FPGA_AD
- 基于Altera的FPGA开发的基于FPGA的AD转换功能，完全通过验证。-Altera s FPGA-based development of FPGA-based AD conversion function, fully validated.
VHDL
- 已经开发成产品的步进电机定位控制系统的VHDL程序-Has developed into a product positioning stepper motor control system VHDL procedures
adc
- vhdl实现对模数转换芯片adc0832的控制,程序采用的是状态编码输出.-VHDL realization of analog-digital conversion chip adc0832 control, procedures using state of the output encoding.
步进电机及伺服电机的控制
- 本程序采用vhdl语言对步进电机及伺服电机进行控制，控制方式灵活，有变速，正反转，显示等多个模块-This procedure using VHDL language of stepper motor and servo motor control, control flexibility, have variable speed, positive, showing a number of modules, etc.
f6lift
- 不同于网上的四层电梯，这是六层电梯的模拟程序，也是现在学校要求的，vhdl语言开发，在板子上运行良好-vhdl 6 lift
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
DS18b20VHDL
- 自己写的一个测温元件（ds18b20）的驱动程序，这是一个完整的读出温度VHDL程序，并且包含ds18b20的中英文参考资料-Writing their own, a temperature measurement device (ds18b20) the driver, when a complete read out the temperature of VHDL procedures and contains reference materials in both English and
LVDS_Serdes_list_FPGA1
- FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
lai_PWM
- FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
DPD_LUT
- 一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT