资源列表
syn_frame
- 基于verilog的帧同步搜索,fpga中可以实现帧头搜索，进而实现同步，并有一定的容错能力-verilog-based frame synchronization searching
VHDL_code_for_DAC_controller
- 一个VHDL代码设计时，它是控制 在AD7524数字至模拟转换器-An VHDL code designs are presented ,it is for controlling the AD7524 digital-to-analogue converter
aludesign
- In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmatic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one
counter
- VHDL常用的计数器模块，包括各种类型的计数器，可供参考-commonly used VHDL modules, including counters, decoders, encoders, latches, etc., can be used as reference
attachments_15_02_2011..
- mod10 counter in vhdl
Guassian-Algorithem
- Gaussian Algorithem for G-Gaussian Algorithem for GMM
Event-capture
- 代码功能：在DSP2812平台上用C语言进行开发实现利用事件管理器EVA中捕获单元的捕获输入引脚检测两个事件变化的时间，即用捕获引脚CAP4检测手动按下开关的时间,至少五次，将两个捕获引脚每次变化是定时器的值存入数据区，手动开关计数值存入200H单元开始的数据区。-Code function: In DSP2812 platform using C language developed to use the Event Manager EVA capture unit to capture in
SpiLoopBack
- DSP2812的SPI模块回读程序，希望对大家有所帮助-The DSP2812 SPI module back to read the program, we hope to help
fdiv
- 频率计的一个模块，即分频器模块，提供的标准信号是48MHz 输出四个信号1Hz，10Hz， 100Hz，1KHz -Frequency of a module that divider module provides the standard signal 48MHz to output four signal of 1Hz, 10Hz, 100Hz, 1KHz
chaoqianadd6
- 用VHDL设计的超前六位加法器，实现六位二进制数的加法操作。-Adder VHDL design ahead of six, six binary addition operation.
DISPLAY_CONTROL
- 并行数码管控制文件。可根据此文件自行扩充至任意位数码管。-Parallel digital control file. This file can be expanded according to their own arbitrary digital tube.
usb_packet_fifo
- usb packet fifo VHDL