资源列表
WATCHDOG
- WATHCHDOG 代码，功能足够强大，公司级应用也可，适合有一定基础的学习。-WATHCHDOG code, powerful enough to company-level applications, suitable for a certain basis for learning.
4wei-ji-shu-qi
- 4位同步二进制加法计数器的工作原理是指当时钟信号clk的上升沿到来时，且复位信号clr低电平有效时，就把计数器的状态清0。 在clr复位信号无效（即此时高电平有效）的前提下，当clk的上升沿到来时，如果计数器原态是15，计数器回到0态，否则计数器的状态将加1. -4 synchronous binary adder counter works by the rising edge of the clock signal clk, and the reset signal CLR acti
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
CD1_MT9V034C_DISPLAY_SAVE
- 基于FPGA的CMOS图像传感器（MT9V034）显示并保存图像-FPGA-based CMOS image sensor (MT9V034) and save the image
tkzc
- verilog hdl蜂鸣器演奏天空之城-the Verilog HDL buzzer playing Castle in the Sky
MAX1037_ADC
- fpga控制ADC max1037.采用openbus设计方法。通过I2C来读取ADC的数据-FPGA to control the ADC MAX1037 the OpenBus design method. To read through the I2C ADC data
ad_max11046
- 基于nios2系统的mx11046的初始化，采样，写命令，读数据，以及一些优化设置。-Based on mx11046 nios2 system initialization, sampling, write commands, read data, and some optimization Settings
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
sing
- 实现了蜂鸣器唱歌的功能，并在FPGA开发板上实现-Realized the function of buzzer singing and implementation on FPGA development board
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
CycloneIII_EP3C40F780C8_8_UART
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,UART 实验代码-SOPC,CycloneIII，EP3C40F780C8，UART code
4fsk-Verilog-HDL
- 基于Verilog HSL的4psk调制解调-very nice