资源列表
surfDispStr
- 这个可实现16色字符定位显示。文本模式下的字符显示。-this can be achieved 16 characters color display orientation. Text mode of the characters shown.
syn_frame
- 基于verilog的帧同步搜索,fpga中可以实现帧头搜索，进而实现同步，并有一定的容错能力-verilog-based frame synchronization searching
aliasing
- This program illustrates the effect of alising of frequency leading to signal distortion,the output graph illustrates frequency respose due to alliasing,easy for students learning DSP
VHDL_code_for_DAC_controller
- 一个VHDL代码设计时，它是控制 在AD7524数字至模拟转换器-An VHDL code designs are presented ,it is for controlling the AD7524 digital-to-analogue converter
aludesign
- In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmatic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one
counter
- VHDL常用的计数器模块，包括各种类型的计数器，可供参考-commonly used VHDL modules, including counters, decoders, encoders, latches, etc., can be used as reference
attachments_15_02_2011..
- mod10 counter in vhdl
dsp
- 由DSP输出脉冲对步进电机进行启动、制动、相位、方向、速度、位置等控制。例如：设计程序，使步进电动机实现间断性步进（30步，间隔0.5秒）→连续正转（60步，间隔0.1秒）→停顿（2秒）→反向间断性步进（30步，间隔0.5秒）→连续反转（60步，间隔0.1秒）。-By DSP for step motor output pulse to start, brake, phase, direction, speed, position control. For example: design pro
Guassian-Algorithem
- Gaussian Algorithem for G-Gaussian Algorithem for GMM
Event-capture
- 代码功能：在DSP2812平台上用C语言进行开发实现利用事件管理器EVA中捕获单元的捕获输入引脚检测两个事件变化的时间，即用捕获引脚CAP4检测手动按下开关的时间,至少五次，将两个捕获引脚每次变化是定时器的值存入数据区，手动开关计数值存入200H单元开始的数据区。-Code function: In DSP2812 platform using C language developed to use the Event Manager EVA capture unit to capture in
SpiLoopBack
- DSP2812的SPI模块回读程序，希望对大家有所帮助-The DSP2812 SPI module back to read the program, we hope to help
fdiv
- 频率计的一个模块，即分频器模块，提供的标准信号是48MHz 输出四个信号1Hz，10Hz， 100Hz，1KHz -Frequency of a module that divider module provides the standard signal 48MHz to output four signal of 1Hz, 10Hz, 100Hz, 1KHz