资源列表
PISO
- It is then register ( shifter) PISO ( Parallel - in, serial - out)-It is then register ( shifter) PISO ( Parallel- in, serial- out)
WM_8776
- WM8776控制模块，直接调用为24位、44.1KHZ采样和输出，开启耳机输出。如需更改可将DA，AD和控制模块分别独立-WM8776 control module, a direct call for the 24-bit, 44.1KHZ sampling and output, open the headphone output. For a change can be DA, AD and control modules separately
Game1
- Game uses LEDS. 2 players participate and push button.
divider
- 基于FPGa的32为除法器，从别的地方搞来的，给大家共享以下，算是做贡献。-Divider based on the FPGA 32, to engage in from somewhere else, to share the following to be considered to contribute to.
TCD
- 基于FPGA的线阵ccd的TCD1501D的verilog驱动。-The verilog drive based on FPGA linear array the ccd' s TCD1501D the.
ADC8C
- It is the program for ADC 8-channel for 8051.
simple_dual_port_ram_single_clock
- Simple Dual-Port RAM with different read/write addresses but single read/write clock
1
- 基于DSP的FIR滤波器设计-DSP-based FIR filter design
encoder
- libs for encoder using -libs for encoder using
SSD1306
- OLED Initialization code，for ssd1306. SSD1306.C-OLED Initialization code，for ssd1306
IOC
- 对MC9S12XS128单片机的定时器的输入捕获功能进行配置，下降沿触发-MC9S12XS128 microcontroller timer for input capture function can be configured to trigger on the falling edge
counter10
- 十进制计数器，比较简单，比较容易，希望大家不要见怪-decimal counter