资源列表
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
HDL
- 这是一个高手写的关于如何提高HDL的编程能力，很有好处的。-This is a master to write about how to improve the capacity of HDL programming, it is beneficial.
cx
- 编码器正反转鉴相及旋转计数，数码管显示哎哎啊-Counting phase
PLC
- VB和三菱PLC通信，PLC控制电机正反转。可实现两轴电机正传翻转停止功能-VB and Mitsubishi PLC communication, PLC control motor reversing. Story of two-axis motor to achieve flip stop function
counter
- 这是一个计数器的代码，用vhdl编写，实现循环技术功能-this is a counter used to count numbers in vhdl
toplevel_png
- top level for ping pong game on vhdl
AD7656
- 6通道、16位高速数模转换芯片AD7656的初始化程序，可作为单片机的片外AD，实现数据采集的功能-6-channel, 16-bit high-speed digital-to-analog conversion chip AD7656 initialization procedure, can be used as a single-chip chip AD, data acquisition functions
485
- 三星S5PV210开发板 485通讯代码-The Samsung S5PV210 development board 485 code
DCMTRTEST
- 直流电机控制实验-DC motor control experiment
uart2
- 基于STC系列单片机进行第二串口的通信测试程序。-test code about the second UART
clk1hz
- 分频电路 将电路分频为1赫兹 可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
CRC32_D82
- CRC 校验 // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit is D[7]- // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit i