资源列表
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
crc_verilog_xilinx
- CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
等精度频率计
- 使用vhdl语言写的fpga的应用程序，使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
COUNT_100
- 使用Vhdl语言编写的FPGA应用程序，实现的内容是100进制计数器-use Vhdl language FPGA applications, realizing the contents of the 100 NUMBER
20051113130721803
- USB-BLASTER原理图，用于Altera可编程芯片的下载-USB-BLASTER schematics, Altera programmable chips for download
20051113104111170
- FPGA的VHDL设计经验总结《小型微型计算机系统》2003年7月-FPGA VHDL design experience, "small micro-computer system," July 2003
EPP
- 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
ModelSim_SE_6.1bkey
- ModelSim SE 6.1 (电子仿真)具体破解-ModelSim SE 6.1 (electronic simulation) Specific crack
Verilog_traffic
- Verilog 的交通灯的例子。源代码中有详细的注释。-Verilog traffic lights examples. The source code for detailed comments.
alu_inverter
- 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
LED七段译码
- 初次上传文件，采用文本格式编辑内容，不知道是否妥当，如有不便之处，敬清各位原谅。-initial upload documents using text format editorial content, I do not know whether they are appropriate, if any inconvenience, King - forgive me.
arith_lib-1.0
- 包括所有常用算法：加权计算，进制转换，常用数据编码等，大约共有源代码80个。-include all commonly used algorithms : weighted basis, the base for the conversion, common data coding, source code, a total of about 80.