资源列表
用VHDL实现布斯算法
- 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
Sparc_leon_VHDL
- 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
8051inVHDL
- 一个8051的VHDL代码，可完整编译， 但不保证版图映射成功，可作为设计微处理器的参考-a 8051 VHDL code can be compiled integrity, but it does not guarantee success territory mapping, the microprocessor can be used as a reference design
VHDL_freerisc8
- 一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。-an eight RiSC SCM VHDL code, is a good reference value.
VHDL_100Examples
- 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
tbcpu8bit2
- 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
uart2
- uart 通用异步接受机 编译环境为quartus-UART Universal Asynchronous Receiver and build environment for Quartus
conv_code
- 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3) - Convolutional Codes.
Traffic_Light_Final
- Traffic light written with Verilog-written with Verilog
final_code
- mining source code written in Verilog
Modelsim上机指导
- 一本详细讲解有关modelsim操作的教程,非常适合初学者.-a modelsim explain in detail the operation of the guides, very suitable for beginners.
Butterworth_IIR_Filter
- DSP中巴特沃思滤波器的设计使用Verilog编写.