资源列表
sale2
- sale，自动收获机。首先投币，然后买东西，然后退币-sale, automatic harvester. The first coin, and then buy something, and then coin
66_FIR
- 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
VHDL数学运算库1.0
- 这是一个VHDL写的数学运算的硬件设计库，还算比较完整-This is a VHDL write arithmetic hardware design basement, still relatively complete
std_cf_2c35
- 这个是基于NIOS II的FPGA平台的一个CF卡的接口模块，是在Quartus II下的完整工程包-NIOS II FPGA platform a CF card interface module, Quartus II is the complete package works
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
Example-2-1
- 这些是verilog的开发实例,仅供参考.实例1-These are examples of the development of Verilog, for reference purposes only. Example 1
Example-2-2
- 这些是verilog编程实例2,仅供参考-These are two examples of Verilog Programming for reference
Example-2-3
- 这些是verilog编程实例3,仅供参考-These are three examples of Verilog Programming for reference
Example-2-4
- 这些是verilog编程实例4,仅供参考-These are four examples of Verilog Programming for reference
Example-2-5
- 这些是verilog编程实例5,仅供参考-These are examples of Verilog Programming 5 for reference
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
WERDTEST
- CCD DRIVER 本软件用于线性CCD 传感器时序控制 -CCD DRIVER software for the linear CCD sensor timing control