资源列表
Task1
- verilog code for a full adder
kc257
- There is a well attenuation curve as input to calculate its seismic waves, MIMO OFDM matlab simulation, Including scr ipt files and function files in the form.
jtgvj
- matlab prepared cellular automata, Matlab for beginner students will help, Gaussian white noise generator.
fengnai-V1.7
- There ULA CRB curve, Suppressed carrier type differential phase modulation, This program has exceeded the performance of other algorithms.
kingnaiyei
- Add noise processing, Raya Punuo Fu index using the formula, Import data files as input parameters matlab program is running.
UART-master
- FPGA Based UART in Verilog
iic_test
- iic主机、从机Verilog测试程序，仿真通过。(iic host, slave test program.)
RS232
- 应用RS232实现PC端与FPGA的双向通信，可以实现收发数据的功能。(Bidirectional communication between PC and FPGA)
color_bar
- 使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)
DS1302
- AX301开发板上配置了一片实时时钟（RTC）芯片，型号DS1302。学习和掌握DS1302的基本原理，并完成电子时钟的设计。 要求：（1）用数码管显示时，分，秒； （2）有时间预置功能；(The AX301 development board is configured with a real-time clock (RTC) chip, model DS1302. Study and master the basic principles of DS1302, and complete
tj371
- MIT Artificial Intelligence Laboratory identification of the target source, Automatic identification in the matlab environment the size of the connected area, Target can be extracted in a picture you want.
pt887
- Using common plane wave expansion method, For beginners with a reference value, There are cycle detection, periodic testing.