资源列表
tcpjs
- LCMV optimization design array signal processing, Gabor wavelet transform and PCA face recognition code, Fractal dimension calculation algorithm matlab code blankets.
megan_fox
- kszzwezrgf wdgasgd wuegfgsgf wuwugdsd
VGA
- 基于FPGA的VGA实验测试及各种代码，希望能对大家有帮助！(FPGA based VGA experimental testing and a variety of code, in the hope that we can help!)
chuankou
- 此文件是一个串口verilog程序，一次传输一个字节，使用quartus编写(This is a program that is written in Verilog language ,It is a Serial program ,You can transfer and return a byte data.)
pulse
- 这是一个方波程序，在quartus平台编写，可以通过设置参数生成方波信号。(This is a square wave program, written in the quartus platform, you can generate square wave signals by setting parameters.)
4_led_test
- 关于FPGA的基于EP4CE6的流水灯程序(The Water lamp program of FPGA)
E3_1
- 测试有符号和无符号二进制数相加结果对比，并对结果进行sim仿真(Test, signed and unsigned binary number addition, result comparison)
E4_6_FirIpCore
- 对软件自带的fir 核进行相关配置，仿真测试其功能，同时完成相关滤波作用，观察其输出波形(The configuration of the fir kernel is simulated, the function is tested, the function of correlation filtering is observed, and the output waveform is observed.)
E4_7_IIRCas
- 完成iir滤波器的相关设计，同时利用数据测试该模块的正确性，对其进行仿真，观察其波形。(Complete the design of IIR filter, and use the data to test the correctness of the module, to simulate it and observe its waveform.)
用vhdl写实用96例子
- 用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
不用IP核设计乘法器
- VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)
xapp1014-xilinx-sdi
- xilinx FPGA实现SDI接口输入输出(SDI in/out with xilinx FPGA)