资源列表
EDAadd
- 全加器Full adder schematic waveform diagram(Full adder schematic waveform diagram)
软件工程 copy
- 熟悉编码、译码器、数据选择器等组合逻辑功能模块的功能与使用方法 掌握用MSI设计的祝贺逻辑电路的方法(Familiar with the functions and application methods of combinational logic function modules, such as code, decoder, data selector, etc. Mastering the logic circuit of congratulation logic circuit d
LCD1602_UART
- kc705上的1602显示模块的verilog源码，以及UART源码，附带一些设计过程资料(kc705 1602 display module source code,and UART source code.addition to some design progress document.)
MAX
- DFSGAAFDGFGHFHSHFSDHFHSH(GSFDGSDFGSFGSFGSGSFGSGSGFSGS)
LCD12864
- VHDL已经在CPLD_EPM240调试OK,,LCD12864显示英文(VHDL has debugged OK in CPLD_EPM240, and LCD12864 shows English)
Convolution
- 卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)
Chapter4
- Digital Design Verilog
27个FPGA实例源代码
- 一些对初学者比较实用的源码，ASK，PSK，FSK调制解调(Some of the more practical source code for beginners)
Tutorial2
- adder4bit scheme, full adder, half adder, and practice
2F
- testing testbench to device under test (dut)
led
- 利用计数器设计延时函数，通过四个led灯的闪烁，可以直观观察延时时长，fpga器件cyclone iv LCMXO2-1200HC-4TG144CR1,在demo板上作简路图(Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-12
traffic
- 交通灯设计，用verilog语言来实行，不包含设计原理图(aknsh s kjsf kwfh jfls ljfsl s lfjls jlsj ls jlf l ljfs ljljl f jljl ljjlsfj ljlsfj ljsflhig)