资源列表
Greedy_snake
- 贪吃蛇，用SPARTAN6系列FPGA实现的贪吃蛇例程，用ISE14.7打开即可，Verilog语言(greedy_snake.rar The realization of the snake in the Verilog language Using ISE14.7)
51CTO下载-VerilogHDL程序设计实例详解12
- VerilogHDL 程序设计实例详解(VerilogHDL program design example detailed solution)
2mw PMSG Complete data
- ndbnfbwfnbbfwhdbfhhwdbhfhbhdhsfbubhb
Mashayan
- rebuild file in check for
hdlsrc
- cONVERTER FROM MAT TO HDL
UART
- 本人用verilog编写的UART协议，经测试可用。(I am prepared to use verilog UART protocol, the test is available.)
S02_CH02_MIO
- xilinx zynq的mio口测试工程，内容很详细(zynq mio test,about zynq mio pin test,very useful)
cordic_xls_1-0
- this cordic is bravo you should redd this
Reference Designs Docs
- ml605_BIST_pdf_xtp056_12.3 ml605_fmc_xm104_ibert_pdf_xtp091_12.3 ml605_getting_started_guide ml605_IBERT_pdf_xtp046_12.3 ml605_MIG_pdf_xtp047_12.3 ml605_multiboot_pdf_xtp043_12.3 ml605_PCIe_Gen1_x8_pdf_xtp044_12.3 ml605_PCIe_Gen2_x4_pdf_xtp045
MAC网络控制的物理层控制程(VHDL)
- MAC网络控制的物理层控制程(VHDL)(The physical layer control of MAC network control (VHDL))
cpu_uart_leds_ip
- 基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
major1_contrast
- code to enhance a picture in verilog.