资源列表
LwIP_socket_apps_sdk
- Vivado sdk socket mode app to implement LwIP
XAPP1026 on the Zedboard
- documentation for LwIP implementation in Zedboard
RISC_CPU
- 一个基于Verilog的cpu 转载于其他网站(A Verilog based CPU is reloaded on other websites)
cy4ex1
- 特权同学FPGA开发板的verilog项目代码(the verilog code project of Tequan Altera cyclone4 FPGA development board)
AES加密算法密码模块
- 其实现了AES加密中的密码模块，包含了功能的说明，模块以及测试用例，学习上手的难度较小(The realization of the AES encryption password module, contains a descr iption of the function modules and test cases, learning difficult to get started)
华为FPGA设计流程指南
- FPGA设计指南，帮助新手快速上手学习FPGA。为以后项目开发垫下基础。(design guide of FPGA)
chuzujifei
- 使用Quartus II 9.0编写的出租车计费系统源码，是课程设计大作业验证通过，可以直接仿真验证(The use of Quartus II 9 written taxis charging system source code, is the course design of large work verification through, can be directly simulated and verified)
FULL_UART
- UART using FPGA implementation
TEXT_TESTING _MOVING
- Banner of a moving characters displaying in tv using vga.
TEXT_TESTING _NATAGOS
- Banner of a passing through characters displaying in tv using vga.
TEXT_TESTING_VAR_SIZED
- Banner of a variable moving characters displaying in tv using vga.
clkdiv
- 该模块是一个常用的clk分频器；其内部参数可以动态调整！(This module is a common CLK frequency divider; its internal parameters can be dynamically adjusted!)