资源列表
1
- curcuit simulation in Hspice
数字钟
- 数字钟(Digital clock)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码，可以使用(ajhsjdhjkshfjhfsjkjksa)
20180125_5M_01
- 基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)
LS165
- LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
count
- 用verilog语言编写一个计数器，改参数实现不同时间的计数器(Writing a counter in the Verilog language)
LS164
- 用verilog原因实现LS164移位寄存器(Implementation of the LS164 shift register with Verilog)
FPGA8 shuma
- 用四位数管显示八位数字并且向左滚动播放。(Four digit tubes display eight digit numbers and roll playback)
vc2015_x64_14.0.24215
- windows 7 安装VIVADO 需要(Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215)
_uart_test2
- data transmitted from FPGA to PC using COM PORT version 2
_spi_test1
- data transmitted from FPGA to devices using SPI bus
add.v
- 这是verilog的加法器。它可用于超大规模集成电路设计。(This is an adder by Verilog. It can be used for VLSI design.)