资源列表
sdram_ov7670_vga
- 利用FPGA采集图像，实现系统检测，很好的采集图像的源代码(Image acquisition using FPGA)
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
Verilog的边沿检测技术_设计源代码
- 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
xapp1052
- 赛灵思官方pcie例程，官网下载需要注册登录，这边给大家另一个选择(Xilinx PCIe official routines, the official website to download the required registration login, here give you another choice)
Vivado 2016.4 SRIO License
- Vivado 2016.4 SRIO License,已经在Vivado 2016.4 测试通过，可以生产位流。其他版本没有测试，估计也是可以用的(Vivado 2016.4 SRIO License, which has been passed in the Vivado 2016.4 test, can produce a bit stream. The other versions are not tested, and the estimates are also available.)
i2c_master_ip_for_nios
- i2c master ip for altera nios, add in qsys
FIFO
- FIFO code in verilog
1800.2-2017
- 最新版 IEEE UVM standard(The newest UVM IEEE standard(2017))
dif
- FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates
shuzizhong
- （1）24小时计时显示（时分秒）； （2）具有时间设置功能（时，分） ； （3）具有整点提示功能； （4）实现闹钟功能（定时，闹响）；((1) 24 hour time display (time, minute, second); (2) have time setting function (time and minute); (3) it has the function of whole point. (4) realize the alarm clock function
1
- 简单的组合逻辑设计，简单分频时序逻辑电路的设计，利用条件语句实现计数分频时序电路(Simple combinatorial logic design, design of simple frequency division sequential logic circuit and Realization of counting frequency division timing circuit by conditional statement)