资源列表
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is
uut_3
- VHDL设计的FIFO 经典结构 功能详尽 敬请参阅(VHDL designed FIFO classic structure functions in detail please refer to)
A4_Clock
- 基于Altera的Cyclone4的时钟程序(clock program based on Cyclone4 of Altera)
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
371231d
- file information such as datasheet
372468a
- fpga documentation regarding something
374566d
- html documents for programming
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
lcd
- lcd屏幕的驱动开发，带偏移，带屏蔽功能显示。(LCD screen driver development, with offset, with screen function display.)
ov7670
- 摄像头ov7670的驱动开发。可通过sccb配置寄存器来选择VGA,QVGA,QQVGA输出。(The driver development of the camera ov7670.The SCCB configuration register can be used to select VGA, QVGA, and QQVGA output.)
sdram
- sdram的驱动开发，支持单字节读写，全页读写，自定义长度读写。(SDRAM drive development, support single byte read and write, full page read and write, custom length read and write.)
ov7670_sdram_lcd
- ov7670采集图像信息，缓存到SDRAM内部，再输出到lcd显示屏来显示出来。(Ov7670 collects image information, caches inside SDRAM, and then outputs it to the LCD display to display it.)