资源列表
DATA_Interleaver
- 这是交织的实现源码 可用于具体的工程实践(This is the interwoven implementation source code that can be used in specific engineering practices)
Verilog的135个经典设计实例
- Verilog HDL的13个经典实例。经过验证，值得学习(The 13 Verilog HDL classic examples. After verification, worth learning)
Verilog典型电路设计_华为
- Verilog典型电路设计,学习价值较高。(Verilog typical circuit design, learning value is higher.)
verilog黄金参考指南中文版
- Verilog设计典型指导资料,学习价值较高。(Verilog design typical guidance information, learning value is higher.)
Verilog-基本语法
- Verilog设计典型指导资料,有学习的价值(Verilog design typical guidance information, has the value of learning)
Gopher360-master
- This iss some ttewtewtewtewt
clocking
- 很好的时钟接口程序，可用于时钟驱动的程序，便于开发者使用(Good clock interface program for clock - driven programs for developers to use.)
crc_core
- 程序主要用来检测或校验数据传输或者保存后可能出现的错误。它是利用除法及余数的原理来作错误侦测的。(The program is mainly used to detect or verify data transmission or to save possible errors.It is an error detection using the principle of division and remainder.)
dsp
- 程序提供特殊的DSP指令，可以用来快速的实现各种数字信号处理算法。(The program provides special DSP instructions, which can be used to quickly implement various digital signal processing algorithms.)
pipelines
- 将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。 将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts. A large operation is decomp
timing_constraints
- 方法能够自动地约束 PLL 的输入和输出时钟。ALTPLL megafunction 中指定的所有 PLL 参数都用于约束 PLL 的输入和输出时钟。(Methods can automatically constrain PLL input and output clock.Named in ALTPLL megafunction.All PLL parameters are used to constrain PLL input and output clocks.)
I2C
- 总线的一些特征:总线应用的例子。极低的电流消耗抗高噪声干扰电源电压范围宽工作的温度范围广(Some features of the bus: examples of bus applications.)