资源列表
分频器
- 对频率实现分频，达到一种对外部的一种分频管理(realization of frequency division)
FIR设计实现sgh
- FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
sd_test
- 基于FPGA的SD卡初始化、读写，实现向FPGA写入数据并读取(SD card initialization, reading and writing, with FPGA based)
SN7474
- 74LS74芯片行为级代码，实现了双D触发器与逻辑延迟，可利用modelsim仿真(74LS74 chip behavior level code)
FP_adder
- 32 bit floating point adder with testbench
FP_divider
- floating point divider for 32 bit with test bench
FP_multiplier
- Multiplier for 32 bit with test bench using verilog HDL
PWN
- Pulse Width modulation using Verilog HDL
ADC_SA_8bit
- the successive approximation part of the circuit. trial_root is loaded with value 8'b1000_0000 on the rising egde that makes count = 3'b000.
4bit_mealy
- Mealy machine is a state machine whose output is determined by the current state and the current inputs.
4bit_moore
- Moore machine is state machine whose output is a function of only the current state.
HDL_equation
- Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop