资源列表
SDRAMPNIOS-II
- 带SDRAM的nios II系统，开发环境为Quartus II 9.0 + Nios II 9.0-With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0
memc_with_fifo
- Verilog编写的Memory Controller代码，用于AMBA总线下-Verilog code written in Memory Controller
UART_DMA
- 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
BCDadd8
- 8位的BCD加法器，BCD表示即4bit表示一个十进制数，取值范围是0000-0110，verilog代码实现-8-bit BCD adder, BCD said that 4bit represents a decimal number, range is 0000-0110, verilog code
MSequenceGenerator
- 5位的M序列发生器，verilog代码实现。5次本原多项式采用f(x)=x^5+x^2+1-5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
DSP-External-Memory-Interface-Module
- EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chi
yimaqi
- 用VHDL实现3-8线译码器的功能，即74HC138-3-8 lines with the VHDL implementation of the decoder function, which 74HC138
Multifunction-digital-clock
- 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Long-frame-synchronous-clock
- 这是长帧同步时钟产生的Verilog源程序，已经编译通过，可以直接使用-This is a long frame sync clock generated Verilog source code, has been compiled by, can be used directly
RS232_LCD_display
- 基于FPGA的RS232串口控制LCD数据显示源程序-RS232 control of LCD display.
dct
- 基于FPGA的图像压缩算法程序，自己写的，可以参考一下-FPGA-based image compression algorithm, write your own, you can refer to
IIR-DIGITAL-NOTCH-FILTER
- IIR数字陷波器的设计文档，可以作为设计陷波器的参考文献-IIR digital notch filter designing document,it can be used as references to design notch filter