资源列表
STCFFTnew
- 用C51通过傅李叶运算在液晶屏上显示音乐频谱，采样是4.47K-Fu Lee leaves with C51 through operations on the LCD display musical spectrum, the sampling is 4.47K
div_verilog
- 基于二进制移位用verilog实现除法的两种方法-Shift based on the binary division with verilog two methods to achieve
8-p-fft
- 基于FPGA和CORDIC算法的8点FFT-8-point FFT based on FPGA and CORDIC
LogicLock
- 通过Quartus软件自带的工程实例——“lockmult”来熟悉Altera Quartus II逻辑锁定功能LogicLock的使用方法。-Comes through the Quartus software engineering examples- " lockmult" to become familiar with Altera Quartus II logic lock LogicLock to use.
DDR2-verilog
- Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code
FPGA-Implementation-of-a-Best-precision-Fixed-poi
- FPGA Implementation of a Best-precision Fixed-point Digital PID Controller
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
ppt4aix4sopc
- 基于AXI4的sopc开发讲义,2011年电子大赛的辅导材料-powerpoint for aix4 sopc development
sunday_clock
- 数字钟 VHDL 年月日 时分秒 东北大学 EDA vhdl例程 电子设计自动化-VHDL date when the digital clock every minute routine Northeastern University Electronic Design Automation EDA vhdl
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
song-play
- 本文作者创新点是基于FPGA完成乐曲演奏电路，在Altera Quartus II 环境下，用VHDL 语言实现电子琴演奏音乐的设计实例，设计者根据VHDL的语法规则，对系统的逻辑行为进行描述，然后通过综合工具进行电路结构的综合、编译、优化，用仿真，可在短时间内设计出高效、稳定、符合设计要求的电路。-This innovation is the author of music to play based on FPGA to complete the circuit, the Altera Qu
pinlv
- 用stm32测fpga输出的频率，带宽可达1Hz-1MHz-Stm32 with the frequency of fpga output, bandwidth of 1 Hz-1 MHz