资源列表
ImageRotate
- verilog实现图像旋转，可终合，并带有Testbench-verilog image rotation, and can be a final, and with Testbench
VHDL
- 表决器 奇校验器 3位比较器 4选1 数据选择器-The odd parity voting 3 comparator election of a data selector
fft16
- 256点的FFT/IFFT变换VERILOG代码核。-256-point FFT/IFFT transform VERILOG code that nuclear.
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
divider
- verilog 实现的除法运算器，可以进行修改。实现更多位宽的数据。-verilog implementation of division operation can be modified. Achieve more wide data.
mydiv
- 实现除法运算的Verilog实现（累加比较法）-The division operation Verilog achieve (cumulative Comparative Law)
100-Power-Tips-for-FPGA-Designers
- 100 Power Tips for FPGA Designers - Stavinov, Evgeni.mobi国外一部比较的书籍-100 Power Tips for FPGA Designers- Stavinov, Evgeni.mobi
Based-FPGA-digital-clock-design
- 基于FPGA的数字时钟设计，这里是我做的一个电子时钟，大家可以借鉴一下！-Based FPGA digital clock design
FPGAgame
- 基于FPGA的俄罗斯方块VHDL逻辑代码，通过VGA显示在液晶屏幕上，基本功能完全实现-VHDL logic code Tetris FPGA-based VGA display on the LCD screen, the basic functions of the full realization of
DA[DA9708]
- FPGA控制DA9708 输出4种常见波形_调频和调幅-FPGA control DA9708 output four kinds of common waveform _ FM and AM
MC8051_IPcore
- 51IP核_VHDL和Verilog编写，并通过编写的C语言源程序进行测试通过-The 51IP the nuclear _VHDL and Verilog, and written in C language source code for testing by
verilong-2048
- 基于FPGA的2048点FFT的verilog实现的源代码大侠们 看吧-erilogand see the source code based on the FPGA 2048-point FFT verilog