资源列表
sdramtest
- vhdl语言编写读写三星SDRAM程序,包含读写控制程序,地址转化程序,测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
dpsk_3rd
- 2DPSK调制与解调。学生实验使用,包括信号源模块、时钟源生成模块、信号调制模块,信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境:Q2 11.0,编译语言:verilog,仿真软件:moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
bianma
- 用verilog编写的实现相位选择的DQPSK调制-Written in verilog DQPSK modulation phase selection
inout-vhdl
- c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
jiaotongdeng
- 简易的交通灯程序,适用于刚接触VHDL的人学习,易懂好学。-Simple traffic light program, for people new to VHDL to learn, easy to understand studious.
prbs
- verilog 格式的prbs数据。可以用于对发射机和接收机的误码率的测试-verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
myfir
- verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件-order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU,这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的,而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
ft2232h_rollback
- FT2232H芯片usb循环读写 verilog 实现, 使用时pll可注释掉-FT2232H the chips usb cycle read and write verilog achieve
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
uvm-1.1d.tar
- UVM World 官方发布的UVM(通用验证方法学)的源代码,基于SystemVerilog,用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
digital_lock
- 数字密码锁verilog源代码,包括键盘输入,控制模块,和显示模块。-Digital code lock verilog