资源列表
ad_max11046
- 基于nios2系统的mx11046的初始化，采样，写命令，读数据，以及一些优化设置。-Based on mx11046 nios2 system initialization, sampling, write commands, read data, and some optimization Settings
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
sing
- 实现了蜂鸣器唱歌的功能，并在FPGA开发板上实现-Realized the function of buzzer singing and implementation on FPGA development board
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
CycloneIII_EP3C40F780C8_8_UART
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,UART 实验代码-SOPC,CycloneIII，EP3C40F780C8，UART code
4fsk-Verilog-HDL
- 基于Verilog HSL的4psk调制解调-very nice
MPPT_PV_12V_FPGA5
- 基于fpga的mppt（最大功率跟踪）无差拍设计-Fpga-based mppt deadbeat designs. . .
fft256_512_1024
- 基于基2的并行256，1024深度的FFT源代码verilog-Based on radix-2 FFT parallel 256,1024 depth verilog source code
RGB0808
- RGB0808矩阵FPGA代码（Verilog HDL语言）-RGB0808 matrix FPGA code (Verilog HDL language)
VGA_FPGA_v8_08
- VGA0808矩阵FPGA代码（Verilog HDL语言）-VGA0808 matrix FPGA code (Verilog HDL language)
led-water
- 流水灯程序，时钟频率为50MHz，控制四个led向同一个方向移动，如流水一样。没建个0.5s点亮一个灯，使灯亮朝一个方向移动-Water lights, clock frequency of 50MHz, control four led moving in the same direction, like water, like. Did not build a 0.5s lit a lamp, the lamp lights move in one direction
UartSend
- FPGA Verilog HDL 语言构建串口数据发送器的详细方案设计-FPGA Verilog HDL language construct serial data transmitter detailed program design