资源列表
xapp1015
- SDI接口的VHDL实现,XILINX官网的设计参考-SDI interface VHDL realize XILINX official website design reference
conv_12_adpcm
- adpcm编码verilog程序,包含pcm转换模块、adpcm编码输出模块-ADPCM coding verilog procedures, including PCM conversion module, ADPCM encoding output module
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含:8位寄存器,5位计数器,32*8 RAM,8位ALU,MUX,顺序控制器,时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
channel_loss
- 数字中频接收机,有助于您加深对多速率信号处理机中频数字接收机设计的理解-IF digital receiver can help U understand the principle of digital receiver.
kechengsheji
- 电子密码锁是基于FPGA实验平台设计的,能够实现密码输入、密码校验、密码设置和更改密码,错误报警和密码错误三次自锁键盘并报警的功能。-Electronic locks, FPGA-based experimental platform can be achieved password entry, password verification, password settings, and change your password, false alarms and the wrong passw
VGA_GAME
- 基于FPGA,VGA,PS2的贪吃蛇游戏verilog源码,内附说明-Based on FPGA, VGA, PS2 Snake game Verilog source code, containing a descr iption
SAR-ADC
- Complete Successive approximation Analog to digital converter along with the source code
CHANNEL_ESTIMATION_PROJECT
- 基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来-Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it
SDK_lwip_echo_server
- Xilinx spartan-3e开发板,EDK的配置,及SDK的一个TCP echo server的实例。运用LWIP(Light Weight IP)轻型IP协议。-Xilinx Spartan-3e development board the EDK' s configuration, and the SDK a TCP echo server instance. The use of the the light IP protocol of LWIP (Light Weight I
clock
- 用 Verilog HDL 设计一个多功能数字钟,包含以下主要功能: 1) 计时,时间以 24 小时制显示; 2) 校时; 3) 闹钟:设定闹钟时间,可利用 LED 闪烁作为闹钟提示; 4) 跑表:启动、停止; 5) 其他。-Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed
nios.ii
- NIOSII开发例程源码包括spi,dma,PIO等-NIOSII development routine source code, including SPI, DMA, PIO, etc.
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL